The present invention relates to semiconductor (integrated circuit) devices and methods of forming the same, and, more particularly, to semiconductor devices including laminated semiconductor layers and methods of forming the same.
Semiconductor (integrated circuit) devices are used in various applications, including microcontrollers, credit cards and the like. Integrated circuit devices can be classified as volatile integrated circuit devices, which typically have fast data input/output speeds but lose data over time. Examples of volatile integrated circuit devices include a dynamic random access memory (DRAM) and static RAM. Integrated circuit devices can also be classified as non-volatile integrated circuit devices, which generally have relatively (compared to volatile devices) slow data input/output speeds but store data permanently. An example of a non-volatile device is a read only memory (ROM). In addition, non-volatile devices have been developed, such as electrical erasable programmable read only memories EEPROMs and Flash memory devices, which can electrically input/output data.
A large storage capacity and high integration in integrated circuit devices has become ever more important as devices including these storage components, such as information communication devices, include ever more advanced functions. Consequently, the size decrease of memory cells, which include integrated circuit devices, has been accelerated in recent years. As the size decrease due to minimization of memory cell sizing, a lithography process commonly used to form such devices is reaching its technical limit. Thus, to overcome this process limit, a method of fabricating a semiconductor integrated circuit device, in which memory cells are laminated in a manner to overlap each other, has been studied so that higher integration can be achieved without further shrinking the size of the memory cell. However, if the height of a memory cell increases due to the laminating of the memory cells in several layers, problems may occur in the patterning procedure for forming contacts. This may cause a significant decrease in the process margin of the contact-forming procedure.